EPISIL
 Subsidiary of EPISIL Holding Inc.
繁體中文
简体中文
English
產品技術
Bipolar Process
CMOS Process
HVCMOS Process
BCD Process
DMOS Process »
GaN Process
SiC Process
Design Service
 
首頁 > 產品技術 > DMOS Process
DMOS Process

 

  0.6μm VDMOS process

The 0.6μm VDMOS process is either a vertical planar or Trench structure, based on a single poly and metal structure. There are completed backend processes available, including back grinding, back metal evaporation, and optional probing/testing service.  Based on the functional demands from customers, functional value-added devices are available to be merged into Episil’s 0.6μm VDMOS, such as poly-diode, poly-fuse and JFET. 

  HV-series VDMOS processes

HV-series VDMOS processes range from 200V to 850V blocking voltage. Guard ring and field plate structure are used in these HV-series VDMOS processes to sustain high blocking voltage.These processes have been widely used in the system of power management, motor control, optical sensor, such as pulse width modulator PWM and anything that needs switching or driving capability.

 Process List

 

 

 

1 Planar

1.2u

0.8u

0.6u

0.6u

30V

30V

30V

200~600V

2 Trench

0.6u

30V

 

© 2015 Episil Technologies Inc.