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CMOS Process

 

  Embedded NVM process

Episil supports its process technologies with highly competitive embedded memory cells, including 0.5μm Flat-cell ROM, and 0.5μm OTP. With the cells, the design company can design its embedded NVM application products to specific density and configuration into 0.5μm Flat-cell ROM and 0.5μm OTP process technology. Embedded NVM process is currently available in 0.5μm Flat-cell and OTP process. High performance and low power consumption are implemented in the embedded NVM design for many consumer ICs, micro-control application products.

  Logic CMOS and Mix-Mode process

Episil offers comprehensive CMOS Logic process for customers to design logic application products. The process technology is based on 0.8 μm. The logic CMOS process,  runnng in 6” line, is based on the single poly and double metal layers structure which allow customers’ design legacy or Pad limited products. A 0.5μm logic process is based on the single poly or double poly (for mix-mode) and double metal /triple metal layers structure running in Episil 6” line. It is suitable for customers to design 0.5 μm logic/mix-mode or for embedding Flat-cell ROM products. The technology documents for these processes are available for customers.

  Low Voltage Logic process

For many portable, low power consumption application products, Episil offers 0.5 μm low voltage process. The layout design rule is the same as 0.5μm/5V application process; the device threshold voltage is lower than the typical 5V CMOS technology. The technology documents are available for customers’application.

 Process List

 

 

 

Logic

0.8u

0.6u

0.5u

1.5V, 3V, 5V

5V

5V

Mix

0.5u

5V, 7V

Flatcell

0.5u

1.5V, 5V

OTP

0.5u

 

 

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